| 发明名称 |
Method and apparatus for memory fault tolerance |
| 摘要 |
One or more circuits may comprise an array of memory cells corresponding to a particular memory address, and a memory fault mitigation module. The one or more circuits may be operable to write a data block to the array of memory cells. The write operation may comprises a swap of a first portion of the data block with a second portion of the data block in response to a detection that one or more memory cells of the array is faulty, and storing the data block to the array of memory cells after the swap. |
| 申请公布号 |
US8897086(B2) |
申请公布日期 |
2014.11.25 |
| 申请号 |
US201313758211 |
申请日期 |
2013.02.04 |
| 申请人 |
|
发明人 |
Ling Curtis;Smolyakov Vadim;Gallagher Timothy;Gulak Glenn |
| 分类号 |
G11C29/04;G11C7/10;G11C29/00;G11C29/44 |
主分类号 |
G11C29/04 |
| 代理机构 |
McAndrews, Held & Malloy, Ltd. |
代理人 |
McAndrews, Held & Malloy, Ltd. |
| 主权项 |
1. A system comprising:
one or more circuits comprising an array of memory cells corresponding to a particular memory address, and a memory fault mitigation module, said one or more circuits being operable to: receive a data block to be written to said array of memory cells; detect whether said data block contains a first type of data or a second type of data; and write said data block to said array of memory cells, wherein:
said data block bypasses said memory fault mitigation module if said data block contains said first type of data; andsaid write comprises a swap, in said memory fault mitigation module, of a first portion of said data block with a second portion of said data block if said data block contains said second type of data. |
| 地址 |
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