发明名称 Data processing device
摘要 A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.
申请公布号 US8898613(B2) 申请公布日期 2014.11.25
申请号 US201414182821 申请日期 2014.02.18
申请人 Renesas Electronics Corporation 发明人 Betsui Takafumi;Taoka Naoto;Suwa Motoo;Matsui Shigezumi;Sugita Norihiko;Fukushima Yoshiharu
分类号 G06F17/50;G11C5/02;G11C5/04;G11C5/06;H05K1/18;H05K3/46;H05K1/02 主分类号 G06F17/50
代理机构 Mattingly & Malur, PC 代理人 Mattingly & Malur, PC
主权项 1. A module comprising: a first substrate; a semiconductor device mounted over the first substrate; a first memory device mounted over the first substrate; and a second memory device mounted over the first substrate, wherein the semiconductor device includes a semiconductor chip; wherein the semiconductor chip has a surface, a first memory interface circuit comprised of a first data unit, and a second memory interface circuit comprised of a second data unit; wherein the surface of the semiconductor chip has a first edge, a second edge facing the first edge, a third edge crossing both the first and second edges, and a fourth edge facing the third edge and crossing both the first and second edges; wherein the first memory interface circuit is arranged along the first edge of the surface of the semiconductor chip in plan view, and arranged closer to the first edge of the surface of the semiconductor chip than the second edge of the surface of the semiconductor chip in plan view; wherein a second memory interface circuit is arranged along the third edge of the surface of the semiconductor chip in plan view, and arranged closer to the third edge of the surface of the semiconductor chip than the fourth edge of the surface of the semiconductor chip in plan view; wherein the first memory device is arranged at the first edge side of the surface of the semiconductor chip in plan view; and wherein the second memory device is arranged at the third edge side of the surface of the semiconductor chip in plan view.
地址 Kanagawa JP