Etch failure prediction based on wafer resist top loss

摘要

An approach for methodology, and an associated apparatus, enabling a simulation process to check integrity of the design and predict a manufacturability of a resulting circuit that accounts for process latitude without a long turnaround time and/or a highly skilled engineer is disclosed. Embodiments include: determining first and second features of an IC design; determining a thickness of a resist layer of the IC design based on an aerial image of the IC design; determining a threshold value according to the thickness; and comparing the threshold value to a separation distance between the first and second features.

主权项

1. A method comprising:
determining first and second features of an integrated circuit (IC) design; determining, prior to a mask write and to wafer print down of a resulting IC circuit corresponding to the IC design, a thickness of a resist layer of the IC design indicated by a profile of an aerial image of the IC design; determining a threshold value according to the thickness by determining a thickness of the resist layer within a region of the IC design containing the first and second features, wherein the threshold value is determined according to the thickness within the region; comparing, by a processor, the threshold value to a separation distance between the first and second features prior to the mask write and to wafer print down; determining a nominal threshold value for the entire IC design, wherein the threshold value is further based on the nominal threshold; and comparing, by the processor, each feature within the region of the IC design with the threshold value; wherein the threshold value is a summation of the nominal threshold value and a weighted value of the thickness.