发明名称 DRAM error detection, evaluation, and correction
摘要 This disclosure includes a method for correcting errors on a DRAM having an ECC which includes writing data to a DRAM row, reading data from the DRAM row, detecting errors in the data that cannot be corrected by the DRAM's ECC, determining erasure information for the row, evaluating the errors using the erasure information, and correcting the errors in the data.
申请公布号 US8898544(B2) 申请公布日期 2014.11.25
申请号 US201213710561 申请日期 2012.12.11
申请人 International Business Machines Corporation 发明人 Franceschini Michele M.;Hunter Hillery C.;Jagmohan Ashish;Kilmer Charles A.;Kim Kyu-hyoun;Lastras-Montano Luis A.;Qureshi Moinuddin K.
分类号 G11C29/00;G06F11/10;G11C29/42 主分类号 G11C29/00
代理机构 代理人 Wilhelm Richard A.;Williams Robert R.
主权项 1. A method for correcting errors in a dynamic random access memory (DRAM) system having associated logic that uses an error correcting code operable to detect and correct a single bit error, and to detect two or more bit errors, comprising: reading data from a row of the DRAM; detecting two or more errors in the data; and in response to the determining of two or more errors in the data: determining whether the row contains one or more weak cells and determining locations of any weak cells in the row, anddetermining whether the weak cells contain errors that can be corrected, and in response to determining that the weak cells contain errors that can be corrected, correcting the errors in the weak cells.
地址 Armonk NY US