发明名称 Power management IC having a power supply PWM that is controllable using either an analog or a digital feedback path
摘要 A Power Management Integrated Circuit (PMIC) includes a pulse width modulator and driver circuit (PWMDC), a processor, and high-side and low-side driver circuitry. The PWMDC, along with components external to the PMIC, forms a switching power supply. A small linear regulator powers the PWMDC from power received via a terminal. The power supply supplies power to other on-chip circuitry, including the driver circuitry and processor. The PWMDC starts an on pulse (of a power supply switching cycle) in response to a clock signal. In a first mode, the PWMDC stops the on pulse based on a signal received from a terminal via an analog feedback signal path. In a second mode, the PWMDC stops the on pulse based on a signal received via a digital feedback signal path. In one example, the digital feedback signal path extends from a terminal, through an ADC, processor, and DAC, to an error node.
申请公布号 US8898491(B2) 申请公布日期 2014.11.25
申请号 US201213461210 申请日期 2012.05.01
申请人 Active-Semi, Inc. 发明人 Huynh Steven
分类号 G06F1/24;G06F15/177 主分类号 G06F1/24
代理机构 Imperium Patent Works 代理人 Imperium Patent Works ;Wallace T. Lester
主权项 1. An integrated circuit comprising: a digital processor that executes instructions; a first sense input terminal; a second sense input terminal; a driver output terminal; and a pulse width modulator and driver circuit (PWMDC) that starts an on pulse by driving a control signal on the driver output terminal to a first voltage level in response to an edge of a clock signal, and in a first mode stops the on pulse by driving the control signal on the driver output terminal to a second voltage level when a first signal on the first sense input terminal has a predetermined relationship with respect to an error signal derived from a second signal on the second sense input terminal, and in a second mode stops the on pulse by driving the control signal on the driver output terminal to the second voltage level when the first signal on the first sense input terminal has a predetermined relationship with respect to a multi-bit digital value received from the digital processor.
地址 VG