| 发明名称 |
Computer or microchip with a secure control bus connecting a central controller to volatile RAM and the volatile RAM to a network-connected microprocessor |
| 摘要 |
A computer or microchip comprising a central controller that connected by a secure control bus with the other parts of the computer or microchip, including a volatile random access memory (RAM) located in a portion of the computer or microchip that is connected to a network. The secure control bus is isolated from any input from the network and provides and ensures direct preemptive control by the central controller over the volatile random access memory (RAM). The direct preemptive control includes transmission of data and/or code to the volatile random access memory (RAM) or erasure of data and/or code in the volatile random access memory (RAM) and includes control of the connection between the central controller and the volatile random access memory (RAM) and between the volatile random access memory (RAM) and a microprocessor having a connection for the network. |
| 申请公布号 |
US8898768(B2) |
申请公布日期 |
2014.11.25 |
| 申请号 |
US201313815814 |
申请日期 |
2013.03.15 |
| 申请人 |
|
发明人 |
Ellis Frampton E. |
| 分类号 |
G06F15/173;G06F13/40;H04L29/06;G06F21/50;G06F21/85;G06F17/00 |
主分类号 |
G06F15/173 |
| 代理机构 |
Mendelsohn, Drucker & Dunleavy, P.C. |
代理人 |
Mendelsohn, Drucker & Dunleavy, P.C. |
| 主权项 |
1. A computer or microchip, comprising:
a central controller of the computer or microchip, including a master controlling device or a master control unit, having a connection by a secure control bus with the other parts of the computer or microchip, including at least a volatile random access memory (RAM) located in a portion of the computer or microchip that has a connection for a network; the secure control bus is isolated from any input from the network; the secure control bus has a configuration by which it provides and ensures direct preemptive control by the central controller over the volatile random access memory (RAM); the direct preemptive control includes transmission of data and/or code to the volatile random access memory (RAM) or erasure of data and/or code in the volatile random access memory (RAM); and the direct preemptive control also includes control of the connection between the central controller and the volatile random access memory (RAM) and between the volatile random access memory (RAM) and at least one microprocessor that has a connection for the network. |
| 地址 |
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