Semiconductor devices having tensile and/or compressive stress and methods of manufacturing

摘要

Semiconductor devices are provided which have a tensile and/or compressive strain applied thereto and methods of manufacturing. The structure includes a gate stack comprising an oxide layer, a polysilicon layer and sidewalls with adjacent spacers. The structure further includes an epitaxially grown straining material directly on the polysilicon layer and between portions of the sidewalls. The epitaxially grown straining material, in a relaxed state, strains the polysilicon layer.

主权项

1. A semiconductor structure comprising:
a relaxed, epitaxially grown straining material on a polysilicon layer of a gate stack structure, wherein:
the gate stack structure is a PFET gate stack structure;the relaxed, epitaxially grown straining material is Si:C; anda lattice constant of the relaxed, epitaxially grown straining material is smaller than a lattice constant of the polysilicon layer of the gate stack structure; a substrate; a second relaxed, epitaxially grown straining material on a polysilicon layer of a second gate stack structure, wherein:
the second gate stack structure is an NFET gate stack structure;the second gate stack structure includes sidewalls and spacers;the second relaxed, epitaxially grown straining material includes a planar surface that is above the second gate stack structure and that extends laterally above the sidewalls and the spacers;the second relaxed, epitaxially grown straining material is SiGe; andan intrinsic lattice constant of the second relaxed, epitaxially grown straining material is larger than a lattice constant of the polysilicon layer of the second gate stack structure; and a shallow trench isolation structure in the substrate between the PFET gate stack structure and the NFET gate stack structure, wherein:
the SiGe material fills a first recess in a source region of the PFET gate stack structure;the SiGe material fills a second recess in a drain region of the PFET gate stack structure; andan oxide cap is formed directly on a top surface of the polysilicon layer of the PFET gate stack structure, the oxide cap having a topmost surface that is within a recess formed in the PFET gate stack structure.