发明名称 Two-stage phase digitizer
摘要 An analog-to-digital converter (ADC) is described. This ADC converts an analog signal into a digital value using a two-pass digitization process. In a first operation, coarse digitization is performed by an averaging converter based on a set of references. Then, in a second operation, fine digitization is performed by either another averaging converter or the same averaging converter based on a subset of the set of references that is progressively closer to an instantaneous value of the analog signal. For example, the coarse digitization may be performed by a low-resolution ADC stage and the fine digitization may be performed by a sigma-delta ADC, such as a single-bit sigma-delta ADC. Moreover, the other averaging converter may use dynamic element matching to shuffle reference elements used to generate the subset. In this way, the ADC may provide high resolution with reduced nonlinearity and quantization noise.
申请公布号 US8896474(B2) 申请公布日期 2014.11.25
申请号 US201313815225 申请日期 2013.02.11
申请人 Stichting voor de Technische Wetenschappen 发明人 Makinwa Kofi A. A.;Van Vroonhoven Caspar
分类号 H03M1/12;H03M3/02;H03M1/14;H03M3/00 主分类号 H03M1/12
代理机构 代理人 Stupp Steven
主权项 1. An analog-to-digital converter (ADC), comprising: an averaging converter configured to receive an analog signal and to output a digital value corresponding to the analog signal based on a set of references, wherein the set of references includes a range of values of the analog signal; and a second averaging converter, electrically coupled to the averaging converter, configured to receive the analog signal and to output a second digital value corresponding to the analog signal based on a second set of references, wherein the second averaging converter is configured to select the second set of references based on the digital value; wherein the second set of references is a subset of the set of references; wherein, in aggregate, the second set of references is closer to an instantaneous value of the analog signal than the set of references; and wherein the averaging converter includes one of: a sigma-delta ADC, a single-slope ADC, a pulse-width modulation ADC, a duty-cycle modulation ADC, and a dual-slope ADC; and wherein the second averaging converter includes one of a second sigma-delta ADC, a second single-slope ADC, a second pulse-width modulation ADC, a second duty-cycle modulation ADC, and a second dual-slope ADC.
地址 Utrecht NL