Time-to-digital converter

摘要

An edge detector includes flip-flops receiving phase signals of a ring oscillator, a resetter canceling the reset states of the flip-flops at the edge timing of an input signal, and a logical operator performing a logical operation on output signals of the flip-flops. A phase state detector detects a phase state of the ring oscillator occurring at the edge timing of the input signal based on the output signals of the flip-flops. A time-to-digital converter converts an edge interval between the input signal and an output signal of the logical operator into a digital value. A latch latches a value of a counter counting the number of cycles of an output signal of the ring oscillator, at the edge timing of the input signal. An operator calculates a digital value of a received signal from output signals of the latch, the phase state detector, and the time-to-digital converter.

主权项

1. A time-to-digital converter for converting an edge interval of an input signal into a digital value, comprising:
a ring oscillator; an edge detection unit including a plurality of flip-flop units configured to receive a plurality of phase signals, respectively, obtained by equally dividing the oscillation period of the ring oscillator, at the respective clock input terminals thereof, a reset unit configured to cancel reset states of the plurality of flip-flop units at the timing of an edge of the input signal and reset the plurality of flip-flop units thereafter, and a logical operation unit configured to perform a logical operation on output signals of the plurality of flip-flop units; a phase state detection unit configured to detect a phase state of the ring oscillator occurring at the timing of the edge of the input signal based on the output signals of the plurality of flip-flop units; a time-to-digital conversion unit configured to convert an edge interval between the input signal and an output signal of the logical operation unit into a digital value; a counter unit configured to count the number of cycles of an output signal of the ring oscillator; a latch unit configured to latch a count value of the counter unit at the timing of the edge of the input signal; and an operation unit configured to calculate a first and a second digital value each containing an output signal of the latch unit in more significant bits, an output signal of the phase state detection unit in intermediate significant bits, and an output signal of the time-to-digital conversion unit in less significant bits, for a first and a second input signal, respectively, successively input to the time-to-digital converter, and calculate a difference between the digital values.