发明名称 Phase locked loop including a frequency change module
摘要 A phase locked loop (PLL) includes a detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO), a divider, and a frequency change module. The detector provides a phase difference based on a reference signal and a feedback signal. The charge pump provides a charge based on the phase difference. The loop filter provides a voltage based on the charge. The VCO provides an output signal based on the voltage received from the loop filter. The divider divides a frequency of the output signal by a value to provide the feedback signal. The frequency change module processes an input signal having a first frequency to provide a processed signal having a second frequency that is different from the first frequency. The frequency change module selects the input signal or the processed signal to provide as the reference signal to the detector. Changing the frequency of the reference signal can change a frequency of a spur.
申请公布号 US8896384(B2) 申请公布日期 2014.11.25
申请号 US201113019046 申请日期 2011.02.01
申请人 Broadcom Corporation 发明人 Chien Hung-Ming
分类号 H03L7/00;H03L7/197;H03L7/23;H03L7/18;H03L7/089 主分类号 H03L7/00
代理机构 Sterne, Kessler, Goldstein & Fox P.L.L.C. 代理人 Sterne, Kessler, Goldstein & Fox P.L.L.C.
主权项 1. A synthesizer, comprising: a phase locked loop (PLL) configured to provide a synthesizer output signal based on a phase difference between a reference signal and a feedback signal; and a frequency change module configured to change a frequency of the reference signal to move a frequency of a spur associated with the synthesizer output signal; wherein the frequency change module includes a switching module configured to receive a first input signal having a first frequency and a second input signal having a second frequency that is different from the first frequency, wherein the switching module is configured to select the first input signal or the second input signal to be the reference signal based on a low pass response of the PLL.
地址 Irvine CA US