Integrated circuit device with reduced leakage and method therefor

摘要

A method includes preferentially placing fill regions adjacent to transistors of a particular conductivity type, such as p-channel transistors, for a plurality of standard cell instances of a device design. The method also includes evaluating all transistors of the first conductivity type prior to evaluating any transistors of a second conductivity type. The second conductivity type is opposite the first conductivity type. For each transistor being evaluated, it is determined whether a criterion is me. A fill region is placed within a field isolation region adjacent to the transistor if the criterion is met.

主权项

1. A method implemented at a computer aided design tool comprising:
preferentially placing fill regions adjacent to transistors of a first conductivity type for a plurality of standard cell instances of a device design to reduce leakage of the plurality of standard cell instances, wherein preferentially placing fill regions further comprises:
evaluating, using a computer, all transistors of the first conductivity type for the plurality of standard cell instances prior to evaluating any transistors of a second conductivity type for the plurality of standard cell instances, the second conductivity type opposite the first conductivity type; andfor each transistor being evaluated, determining if a criterion comprising a design rule that governs surface planarity is met, and placing the fill region within a field isolation region and adjacent to the transistor being evaluated in response to the criterion being met.