| 摘要 |
According to the present invention, a digital signal processor comprises a DRAM including a plurality of memory cells which store data in a parasitic capacitor; and a core logic carrying out date recording, reading, or, renewing of the DRAM based on a predetermined digital signal processing algorithm. The core logic records input data of the memory cell of the DRAM, and then outputs the recorded input data to the outside by reading or stores the input data in another memory cell of the DRAM before retention is passed out. |
