| 摘要 |
<p>An embodiment of the present invention relates to an integrated circuit (IC) package assembly in which multiple dies are three-dimensionally integrated, a corresponding manufacturing method, and a system including the 3D IC package assembly. A bumpless build-up layer (BBUL) package substrate is able to be formed on a first die which is the same as a microprocessor die. A laser beam is able to be used to form an opening on a die backside film (DBF) to expose a TSV pad to the rear surface of the first die. A second die such as a memory die stack is able to be connected to the first die by mutual connecting parts formed between TSVs corresponding to the first and second dies. An underfill material is able to be applied to fill the whole or part of a random residual gap between the first and second dies and/or a capsulized material is able to be applied to the second die and/or package substrate. Other embodiments are able to be described and/or claimed.</p> |
