Parallel Data Switch

摘要

An interconnect apparatus enables improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. An interconnect apparatus can comprise a plurality of logic units and a plurality of buses coupling the plurality of logic units in a selected configuration of logic units arranged in triplets comprising logic units LA, LC, and LD. The logic units LA and LC are positioned to send data to the logic unit LD. The logic unit LC has priority over the logic unit LA to send data to the logic unit LD. For a packet PKT divided into subpackets, a subpacket of the packet PKT at the logic unit LA, and the packet specifying a target either: (A) the logic unit LC sends a subpacket of the packet PKT to the logic unit LD and the logic unit LA does not send a subpacket of the packet PKT to the logic unit LD; (B) the logic unit LC does not send a subpacket of data to the logic unit LD and the logic unit LA sends a subpacket of the packet PKT to the logic unit LD; or (C) the logic unit LC does not send a subpacket of data to the logic unit LD and the logic unit LA does not send a subpacket of the packet PKT to the logic unit LD.

主权项

1. An interconnect apparatus configured to communicate data packets through a network, the data packets arranged in a plurality of sub-packets including an address sub-packet that specifies a target logical unit for receiving the packet, the interconnect apparatus comprising:
at least one logical unit of a plurality of logical units interconnected in a network; and at least one bus coupling ones of the plurality of logical units in a selected arrangement, the at least one logical unit configured to receive the address sub-packet and determine routing based on:
(1) header information specified in the address sub-packet and(2) control information received from logical units in a subset of logical units distinct from the at least one logical unit.