DYNAMIC SET ASSOCIATIVE CACHE APPARATUS FOR PROCESSOR AND ACCESS METHOD THEREOF

摘要

The present invention provides a dynamic set associative cache apparatus for a processor. When read access occurs, the apparatus first determines a valid/invalid bit of each cache block in a cache set to be accessed, and sets, according to the valid/invalid bit of each cache block, an enable/disable bit of a cache way in which the cache block is located; then, reads valid cache blocks, compares a tag section in a memory address with a tag block in each cache block that is read, and if there is a hit, reads data from a data block in a hit cache block according to an offset section of the memory address.

主权项

1. A dynamic set associative cache apparatus for performing read access, the apparatus comprising:
a memory configured to store instructions; and a processor coupled to the memory and configured to execute instructions to:
(1) locate, according to an index section of a memory address, a cache set to be accessed, wherein a tag section is included in the memory address,(2) obtain a valid cache block whose valid/invalid bit is valid in the cache set to be accessed by checking a pre-set table unit, wherein the table unit includes a valid/invalid bit of a cache block,(3) set an enable/disable bit of a cache way, in which the valid cache block is located, to enable, and(4) read, according to the enable/disable bit, the valid cache block in the cache set, wherein the valid cache block includes a tag block and a data block, and reading data from a data block in a valid cache block whose tag block matches the tag section in a memory address.