HARDWARE UNIT FOR FAST SAH-OPTIMIZED BVH CONSTRUTION

摘要

A graphics data processing architecture is disclosed for constructing a hierarchically-ordered acceleration data structure in a rendering process. The architecture includes at least first and second builder modules, connected to one another and respectively configured for building a plurality of upper and lower hierarchical levels of the data structure. Each builder module comprises at least one memory interface with at least a pair of memories; at least two partitioning units, each connected to one respective of the pairs of memories; at least three binning units connected with each partitioning unit and the memory interface, one binning unit for each of the threes axes X, Y and Z of a three-dimensional graphics scene; and a plurality of calculating modules connected with the binning units for calculating a computing cost associated with each of a plurality of splits from a splitting plane and for outputting data representative of a lowest cost split.

主权项

1. A graphics data processing architecture for constructing a hierarchically-ordered acceleration data structure in a rendering process, comprising:
at least two builder modules, consisting of at least a first builder module configured for building a plurality of upper hierarchical levels of the data structure, connected with at least a second builder module configured for building a plurality of lower hierarchical levels of the data structure; and wherein each builder module comprises at least one memory interface comprising at least a pair of memories; at least two partitioning units, each connected to one respective of the pairs of memories and configured to read a vector of graphics data primitives therefrom and to partition the primitives into one of two new vectors according to which side of a splitting plane the primitives reside; at least three binning units connected with each partitioning unit and the memory interface, one binning unit for each of the threes axes X, Y and Z of a three-dimensional graphics scene, and each configured to latch data from the output of the pair of memories and to calculate and output an axis-respective bin location and the primitive from which the location is calculated; and a plurality of calculating modules connected with the binning units for calculating a computing cost associated with each of a plurality of splits from the splitting plane and for outputting data representative of a lowest cost split.