| 摘要 |
A display device includes: a pixel array unit with pixel circuits disposed in matrix form, the pixel circuit including a driving transistor, an electro-optic element, a storage-capacitor, and a sampling transistor, with the electro-optic element emitting light by generating a driving current based on information stored in the storage-capacitor at the driving transistor to be applied to the electro-optic element; and a control unit, of which the output stage includes a buffer transistor, to output a pulse signal for driving the pixel array unit from the buffer transistor; wherein the pixel array unit and the control unit are formed with long laser beam irradiation to be scanned in the vertical direction; and with the control unit, buffer transistors for outputting a pulse signal for sampling to an input video signal to each signal line are arrayed in a column in the longitudinal direction of the laser beam irradiation. |
| 主权项 |
1. A display device comprising:
a pixel array unit including a plurality of pixel circuits disposed in a matrix having a row direction and a column direction, at least one of said pixel circuits comprising
a driving transistor configured to control a driving current,a storage capacitor configured to store a signal corresponding to a signal potential of an image signal supplied via an image signal line and a sampling transistor, andan electro-optic element configured to emit light in accordance with the driving current, the driving current being based on the signal stored in said storage capacitor and being received through the driving transistor and a first switching transistor; and a control unit having an output stage that includes a first buffer transistor and a second buffer transistor configured to output a pulse signal for driving said pixel array unit,wherein
the first buffer circuit is configured to output a first pulse signal to the sampling transistor and the second buffer circuit is configured to output a second pulse signal to the first switching transistor, the first buffer comprises a first transistor and a second transistor configured to be switched complementally, and the second buffer comprises a third transistor and a fourth transistor configured to be switched complementally, a gate electrode of the first transistor and a gate electrode of the third transistor are arranged along the row direction, each of a channel of the first transistor and second transistor are arranged along the column direction, each of a channel of the third transistor and fourth transistor are arranged along the column direction, and the first buffer and the second buffer are connected to the same pixel circuit. |
