发明名称 METHOD FOR PROVIDING GATE METAL LAYER OF TRANSISTOR DEVICE, AND ASSOCIATED TRANSISTOR
摘要 <p>PROBLEM TO BE SOLVED: To more superiorly control a threshold voltage.SOLUTION: On a substrate, a dummy gate structure is provided which comprises a gate dielectric layer 2 and a dummy gate electrode layer and is defined in a lateral direction by inner sidewalls 322 of spacer couples 311 and 321. The dummy gate structure is embedded in a lateral direction, the dummy gate electrode layer is removed and between the inner sidewalls of the spacer couples, a final gate electrode layer is provided which is replaced with the dummy gate electrode layer. In the step of providing the final gate electrode layer, a connected diffusion layer is provided (which extends or exists at least on the gate dielectric layer, on the inner sidewalls of the spacer couples and on a part of a front face of an embedded layer for a dummy structure) and on the diffusion layer 4, a metal layer 5 containing a metal is provided. Then, an anneal step is applied which is prepared to energize the diffusion of the metal into the diffusion layer and to diffuse the metal within the diffusion layer to a diffusion layer portion in a region corresponding to a gate dielectric region, and while using a final gate metal filling layer, a region between the inner sidewalls of the spacer couples is filled.</p>
申请公布号 JP2014220496(A) 申请公布日期 2014.11.20
申请号 JP20140086568 申请日期 2014.04.18
申请人 IMEC 发明人 TOGO MITSUHIRO
分类号 H01L21/336;H01L21/28;H01L21/8234;H01L21/8238;H01L27/088;H01L27/092;H01L29/41;H01L29/78;H01L29/786 主分类号 H01L21/336
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