Arithmetic apparatus including multiplication and accumulation and DSP structure and filtering method using the same

摘要

PURPOSE: An operating apparatus including MAC(Multiplication and Accumulation) operation and DSP(Digital Signal Processor) structure and filtering method thereof are provided to reduce the resource consumption of the DSP and enhance the whole operation ability by performing the MAC operation having the two times precision. CONSTITUTION: A first and second register(110,120) stores the n-bit data. A third register(130) stores 2n- bit data. A multiplier(140) receives the data of the first register through a first input node and receives the data of the second and third register through a second input node. The multiplier multiplies the received data from the first and second input node. An ALU(Arithmetic Logic Unit)(150) receives the operation value of the multiplier through the first input node, adds the received values from the first and second input node, and transfers the added value to the third register. The operation value of the ALU is transferred to the second input node of the ALU.