SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF TESTING SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

A semiconductor integrated circuit is provided with: a memory under test; a test-result-storage memory; a test-data generation part for generating in a sequential manner a test address signal and test data for supplying to the memory under test; and a control circuit. The control circuit includes a delay circuit, which, when the control circuit stores in a sequential manner in the test-result-storage memory a test result according to the test address signal and test data in the memory under test, delays the storage-destination address signal in the test-result-storage memory from the test address signal set in the memory under test, in accordance with a time delay that includes at the least the latency from the setting of the test address signal in the memory under test to the reading out of the test data.

主权项

1. A semiconductor integrated circuit comprising:
a test target memory; a test result storage memory; a test data generating unit to sequentially generate a test address signal and test data to be supplied to the test target memory; and a control circuit including a delay circuit to delay, when sequentially storing in the test result storage memory test result data based on the test address signal and the test data supplied to the test target memory, a storage destination address signal to be supplied to the test result storage memory than the test address signal to be supplied to the test target memory, in accordance with a time delay containing at least a latency between supplying the test address signal to the test target memory and reading corresponding test result data.