发明名称 REDUCING SETTLING TIME IN PHASE-LOCKED LOOPS
摘要 A circuit may include a phase detector configured to generate a phase error signal based on a feedback signal and an oscillator configured to generate an output signal. The feedback signal may be based on the output signal. The circuit may also include a determination unit configured to measure a phase of the feedback signal based on the phase error signal when an output of the phase detector and an input of the oscillator are communicatively decoupled. The circuit may also include an adjustment unit configured to subtract the measured phase of the feedback signal from an intermediate signal upon which the output signal is based when the output of the phase detector and the input of the oscillator are communicatively coupled.
申请公布号 US2014340131(A1) 申请公布日期 2014.11.20
申请号 US201313895139 申请日期 2013.05.15
申请人 Intel IP Corporation 发明人 REY Claudio;HARNISHFEGER David
分类号 H03L7/099 主分类号 H03L7/099
代理机构 代理人
主权项 1. A circuit comprising: a phase detector configured to generate a phase error signal based on a feedback signal; an oscillator configured to generate an output signal, the feedback signal based on the output signal; a determination unit configured to measure a phase of the feedback signal based on the phase error signal when an output of the phase detector and an input of the oscillator are communicatively decoupled; and an adjustment unit configured to subtract the measured phase of the feedback signal from an intermediate signal upon which the output signal is based when the output of the phase detector and the input of the oscillator are communicatively coupled.
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