LOCKING A SYSTEM MANAGEMENT INTERRUPT (SMI) ENABLE REGISTER OF A CHIPSET

摘要

Example embodiments disclosed herein relate to locking a system management interrupt (SMI) enable register of a chipset. Example embodiments include at least one contact configuration register to configure a contact of a chipset, and a contact SMI enable register of a chipset to store an enable value or a disable value. In example embodiments, the disable value stored in the contact SMI enable register is to prevent the chipset from providing an SMI request to a processor in response to an SMI signal received at the contact. Example embodiments further include locking the contact SMI enable register.

主权项

1. A computing device comprising:
a processor; a computing resource to generate a system management interrupt (SMI) signal; and a chipset comprising:
a first contact to receive the SMI signal from the computing resource;at least one contact configuration register to configure the first contact as a general purpose input/output (GPIO) to receive input; anda first contact SMI enable register associated with the first contact, wherein an enable value stored in the first contact SMI enable register is to, in combination with other chipset information, enable the chipset to provide an SMI request to the processor in response to the received SMI signal;wherein the chipset is to lock the first contact SMI enable register; andwherein a disable value stored in the first SMI enable register is to prevent the chipset from providing an SMI request to the processor in response to the received SMI signal.