| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce time till a reset state of a plurality of circuits operating by a different clock signal is released, and to bring timing close when a reset state is released in synchronization with a clock signal among a plurality of circuits.SOLUTION: A first signal synchronization circuit 1 includes a first delay circuit 11, a first gate circuit 12, and a second delay circuit 13. The first delay circuit 11 delays a reset signal RST in synchronization with a first clock signal CLK 1. The first gate circuit 12 outputs a composite reset signal based on AND operation of the first delay signal RST1 showing a rest signal RST delayed by the first delay circuit 11 and another delay signal in which the reset signal RST is delayed. The second delay circuit 13 outputs a first delay reset signal RSTO1 that delays the composite reset signal output from the first gate circuit 12 in synchronization with a first clock signal CLK1.</p> |
