发明名称 SEMICONDUCTOR DEVICE
摘要 A nonvolatile memory is provided. A semiconductor device (a nonvolatile memory) has a circuit configuration similar to that of a general SRAM. By providing a transistor whose off-state current is small between a stored data holding portion and a power supply line of the SRAM, leakage of electric charge from the stored data holding portion is prevented. As the transistor whose off-state current is small provided for preventing leakage of electric charge from the stored data holding portion, a transistor including an oxide semiconductor film is preferably used. Such a configuration can also be applied to a shift register, whereby a shift register with low power consumption can be obtained.
申请公布号 US2014339551(A1) 申请公布日期 2014.11.20
申请号 US201414447897 申请日期 2014.07.31
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 Sekine Yusuke
分类号 H01L27/105;H01L27/11 主分类号 H01L27/105
代理机构 代理人
主权项 1. A semiconductor device comprising a first memory comprising: a first transistor, a second transistor, a third transistor, and a fourth transistor electrically connected to each other in series in order; and a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor electrically connected to each other in series in order, wherein one of a source and a drain of the first transistor and one of a source and a drain of the fifth transistor are electrically connected to a high power supply potential line, wherein one of a source and a drain of the fourth transistor and one of a source and a drain of the eighth transistor are electrically connected to a low power supply potential line, wherein a gate of the second transistor, a gate of the third transistor, a gate of the sixth transistor, and a gate of the seventh transistor are electrically connected to a first terminal, wherein a gate of the fifth transistor and a gate of the eighth transistor are electrically connected to a second terminal, wherein the second terminal is electrically connected between the second transistor and the third transistor, wherein a gate of the first transistor and a gate of the fourth transistor are electrically connected to a third terminal, wherein the third terminal is electrically connected between the sixth transistor and the seventh transistor, wherein each of the first transistor and the fifth transistor is a p-channel transistor, wherein each of the second transistor, the third transistor, the sixth transistor, and the seventh transistor is a transistor comprising an oxide semiconductor layer, and wherein each of the fourth transistor and the eighth transistor is an n-channel transistor.
地址 Atsugi-shi JP