STACKED SEMICONDUCTOR NANOWIRES WITH TUNNEL SPACERS

摘要

A structure is provided that includes at least one multilayered stacked semiconductor material structure located on a semiconductor substrate and at least one sacrificial gate material structure straddles a portion of the at least one multilayered stacked semiconductor structure. The at least one multilayered stacked semiconductor material structure includes alternating layers of sacrificial semiconductor material and semiconductor nanowire template material. End segments of each layer of sacrificial semiconductor material are then removed and filled with a dielectric spacer. Source/drain regions are formed from exposed sidewalls of each layer of semiconductor nanowire template material, and thereafter the at least one sacrificial gate material structure and remaining portions of the sacrificial semiconductor material are removed suspending each semiconductor material. A gate structure is formed within the areas previously occupied by the at least one sacrificial gate material structure and remaining portions of the sacrificial semiconductor material.

主权项

1. A semiconductor structure comprising:
at least one stacked semiconductor nanowire array suspended above a surface of a semiconductor substrate, wherein said at least one stacked semiconductor nanowire array includes a plurality of vertically spaced apart semiconductor nanowires; a tunnel spacer located beneath and at end portions of each vertically spaced apart semiconductor nanowire of said at least one stacked semiconductor nanowire array, wherein a sidewall surface of each tunnel spacer is vertically coincident with a sidewall surface of each vertically spaced apart semiconductor nanowire of said at least one stacked semiconductor nanowire array; a first gate structure located above a topmost vertically spaced apart semiconductor nanowire of said at least one stacked semiconductor nanowire array; and a second gate structure located beneath each vertically spaced apart semiconductor nanowires of said at least one stacked semiconductor nanowire array and located between each tunnel spacer.