发明名称 演算処理装置及び演算処理装置の制御方法
摘要 A processor including: a first storage unit that stores data; an error detection unit that detects an occurrence of error in data read out from the first storage unit; a second storage unit that stores data read out from the first storage unit based on a load request; a rerun request generation unit that generates a rerun request of a load request to the first storage unit in the same cycle as the cycle in which error of data is detected when the error detection unit detects the occurrence of error in data read out from the first storage unit by the load request; and an instruction execution unit that retransmits the load request to the first storage unit when data in which error is detected and a rerun request are given.
申请公布号 JP5625329(B2) 申请公布日期 2014.11.19
申请号 JP20090260950 申请日期 2009.11.16
申请人 富士通株式会社 发明人 白髭 祐治;砂山 竜一
分类号 G06F9/38;G06F12/08 主分类号 G06F9/38
代理机构 代理人
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