发明名称 LSIチップ積層システム
摘要 PROBLEM TO BE SOLVED: To construct an information system which is extremely compact in size, low in power consumption and high in speed, and has high functionality by providing a technology which makes use of the super parallelism of connection lines and combines LSIs in accordance with a purpose to constitute a system. SOLUTION: An LSI chip lamination system includes: a plurality of buses shared between chips 1 and 2 which are connected between chips in a lamination direction by an inter-chip common signal through a via 3 piercing a region common to the chips in the lamination direction; and bus connection switches 11, 12, 21 and 22 which selectively set connection between buses shared between chips 1 and 2 and buses in chip planes 14 and 24 in accordance with switch setting signals transmitted through the buses shared between chips. In the LSI chip lamination system, it is possible to logically and simultaneously perform a plurality of communication by a plurality of control parts 16 and 26 for controlling the buses shared between chips and the bus connection switches controlled by the control parts. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP5626753(B2) 申请公布日期 2014.11.19
申请号 JP20090272225 申请日期 2009.11.30
申请人 发明人
分类号 G06F13/36 主分类号 G06F13/36
代理机构 代理人
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