| 摘要 |
An arithmetic processing unit (10) includes a first cache memory unit (20a) that holds a part of data stored in the storage device; an address register (37) that holds an address;a flag register (31a) that stores flag information;a decoding unit (3B) that decodes a prefetch instruction for acquiring data stored at the address in the storage device; and an instruction execution unit(38a) that executes a cache hit check instruction instead of the prefetch instruction on the basis of a decoded result when the flag information is held, the cache hit check instruction allowing for searching the first cache memory unit (20a) with the address to thereby make a first cache hit determination that the first cache memory unit (20a) holds the data stored at the address in the storage device. |
