发明名称 多重プリフェッチI/O構成を備えるデータパスを有するメモリデバイスおよび方法
摘要 A method of transferring data from a memory array in either a first operating mode or a second operating mode comprises prefetching a first set of 2N data bits in the first operating mode; prefetching a second set of N data bits in the second operating mode; in the first operating mode, transferring the first set of 2N data bits to 2M data bus terminals in respective bursts of N/M bits; and in the second operating mode, transferring the second set of data bits to M data bus terminals in M busts of N/M bits.
申请公布号 JP5625163(B2) 申请公布日期 2014.11.19
申请号 JP20120172023 申请日期 2012.08.02
申请人 发明人
分类号 G11C11/409;G11C11/4096;G11C7/10;G11C11/401;G11C11/407 主分类号 G11C11/409
代理机构 代理人
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