Hardware to support looping code in an image processing system

摘要

An image processing system including a vector processor and a memory adapted for attaching to the vector processor. The memory is adapted to store multiple image frames. The vector processor includes an address generator operatively attached to the memory to access the memory. The address generator is adapted for calculating addresses of the memory over the multiple image frames. The addresses may be calculated over the image frames based upon an image parameter. The image parameter may specify which of the image frames are processed simultaneously. A scalar processor may be attached to the vector processor. The scalar processor provides the image parameter(s) to the address generator for address calculation over the multiple image frames. An input register may be attached to the vector processor. The input register may be adapted to receive a very long instruction word (VLIW) instruction. The VLIW instruction may be configured to transfer only: (i) parameters for image processing calculations over the image frames by the ALU units and (ii) a single bit to the address generator.

主权项

1. An image processing system comprising:
a vector processor (404); and a memory (402) adapted for operatively attaching to said vector processor (404), wherein said memory (402) is adapted to store a plurality of image frames (15), wherein said vector processor (404) includes an address generator (408) operatively attached to said memory (402) to access said memory (402), wherein said address generator (408) is adapted for calculating addresses of said memory (402) over said image frames (15), wherein said address generator (408) is programmed with parameters of an execution loop over the image frames (15), wherein said parameters are selected from a group of horizontal (X) and vertical (Y) image parameters, the group consisting: a horizontal increment value (Xstep), an initial horizontal value (XStart), a horizontal product of the horizontal increment value (Xstep) and a horizontal count iteration value (Xcount), a vertical increment value (YStep), an initial vertical value (Ystart), a vertical product of said vertical increment value (Ystep) and a vertical count iteration value (Ycount), a number of memory addresses (Width) and a memory size value of said memory (402) per image frame (Base); wherein said address generator (408) includes:
a horizontal counter (72X) with a horizontal output of X=X+Xstep, wherein the a horizontal counter 72X has inputs from the horizontal increment value (Xstep) and the horizontal value (XStart);an output of a comparator (74X) connected to another input of the horizontal counter (72X), wherein the comparator (74X) compares the horizontal output of X=X+Xstep with the horizontal product of the horizontal increment value (Xstep) and the horizontal count iteration value (Xcount);a vertical counter (72Y) with a vertical output of Y=Y+Ystep, wherein the vertical counter 72Y has inputs from the vertical increment value (Ystep), the vertical value (YStart) and a signal (DONE) from the horizontal counter (72X);an output of a comparator (74Y) connected to another input of the vertical counter (72Y), wherein the comparator (74Y) compares the vertical output of Y=Y+Ystep with the vertical product of the vertical increment value (Ystep) and the vertical count iteration value (Ycount);
a multiplier (76), wherein a multiplier output of the a multiplier (76) is the vertical output of Y=Y+Ystep multiplied with the number of memory addresses (Width);an adder (78), wherein a first adder output of the adder (78) is the multiplier output added with the horizontal output of X=X+Xstep;a second adder (79), wherein a second adder output (NextADDR) of the second adder (79) is the first adder output added with memory size value of said memory (402) per image frame (Base); wherein said vector processor (404) includes hardware to support looping code during execution, and wherein said address generator (408) is configured to generate a break signal to be received by said hardware to break execution of said looping code of the vector processor (404) over the image frames (15), wherein said break signal is a second output (DONE) of said vertical counter (72Y).