| 发明名称 | Data transmission circuit and data transmission/reception system with reduced jitter | ||
| 摘要 | A data transmission/reception system includes a data transmission circuit and a data reception circuit. The data transmission circuit includes a pattern detection unit configured to detect a pattern of data to be loaded on inner lines among a plurality of transmission lines and generate an inversion signal, and a transmission unit configured to transmit data to the plurality of transmission lines and the inversion signal to an inversion line, and invert some of the data to be loaded on the inner lines in response to the inversion signal. The data reception circuit is configured to invert the data inverted by the transmission unit among the data transferred to the plurality of transmission lines, in response to the inversion signal. | ||
| 申请公布号 | US8891346(B2) | 申请公布日期 | 2014.11.18 |
| 申请号 | US201012833320 | 申请日期 | 2010.07.09 |
| 申请人 | SK Hynix Inc. | 发明人 | Lee Guen-Il |
| 分类号 | H04J1/12;H04J3/10;H04B1/10;H03M5/00;H04B3/32;H04L25/02 | 主分类号 | H04J1/12 |
| 代理机构 | IP & T Group LLP | 代理人 | IP & T Group LLP |
| 主权项 | 1. A data transmission circuit comprising: a pattern detection unit configured to detect a pattern of data to be loaded on two inner lines, among four transmission lines, and generate an inversion signal; and a transmission unit configured to transmit data to the four transmission lines and the inversion signal to an inversion line, and invert some of the data to be loaded on the two inner lines in response to the inversion signal, wherein the inversion signal is in an inactive state when the data to be loaded on one line of the two inner lines and the data to be loaded on the other line of the two inner lines have the same logic value, and the inversion signal is in an active state when the data to be loaded on one line of the two inner lines and the data to be loaded on the other line of the two inner lines have different logic values. | ||
| 地址 | Gyeonggi-do KR | ||