发明名称 |
Apparatus and method for power MOS transistor |
摘要 |
A MOS transistor comprises a substrate, a first region formed over the substrate, a second region grown from the first region, a third region of formed in the second region, a first drain/source region formed in the third region, a first gate electrode formed in a first trench, a second drain/source region formed in the second region and on an opposite side of the first trench from the first drain/source region and a second trench coupled between the second drain/source region and the second region, wherein the second trench is of a same depth as the first trench. |
申请公布号 |
US8890240(B2) |
申请公布日期 |
2014.11.18 |
申请号 |
US201414182001 |
申请日期 |
2014.02.17 |
申请人 |
Taiwan Semiconductor Manufacturing Company, Ltd. |
发明人 |
Ng Chun-Wai;Chou Hsueh-Liang;Su Po-Chih;Liu Ruey-Hsin |
分类号 |
H01L29/66;H01L21/336;H01L21/4763;H01L21/332;H01L29/78;H01L29/10 |
主分类号 |
H01L29/66 |
代理机构 |
Slater & Matsil, L.L.P. |
代理人 |
Slater & Matsil, L.L.P. |
主权项 |
1. A method comprising:
forming a buried layer of a second conductivity over a substrate of a first conductivity; forming an epitaxial layer of the second conductive over the buried layer; applying a first etching process to the buried layer and the epitaxial layer to form a first trench and a second trench, wherein a width of the second trench is greater than a width of the first trench; applying a dielectric deposition process to the first trench and the second trench; applying a second etching process to the first trench and the second trench until a dielectric layer in the second trench has been removed; and forming a first gate region in the first trench and a second gate region in the second trench, wherein a bottom surface of the first gate region is higher than a bottom surface of the second gate region. |
地址 |
Hsin-Chu TW |