Methods and apparatus for non-volatile memory cells with increased programming efficiency

摘要

Methods and apparatus for non-volatile memory cells with increased programming efficiency. An apparatus is disclosed that includes a control gate formed over a portion of a floating gate formed over a semiconductor substrate. The control gate includes a source side sidewall spacer adjacent a source region in the semiconductor substrate and a drain side sidewall spacer, the floating gate having an upper surface portion adjacent the source region that is not covered by the control gate; an inter-poly dielectric over the source side sidewall spacer and the upper surface of the floating gate adjacent the source region; and an erase gate formed over the source region and overlying the inter-poly dielectric, and adjacent the source side sidewall of the control gate, the erase gate overlying at least a portion of the upper surface of the floating gate adjacent the source region. Methods for forming the apparatus are provided.

主权项

1. An method comprising:
providing a substrate; forming a floating gate layer over the substrate and a control gate over the floating gate layer, the floating gate layer having a first portion extending past a first side of the control gate and a second portion extending past a second side of the control gate; forming a first dielectric layer over a first sidewall and a second sidewall of the control gate and over the floating gate layer on the first side and the second side of the control gate; removing a first horizontal portion of the first dielectric layer extending over the first portion of the floating gate layer, a second horizontal portion of the first dielectric layer extending over the second portion of the floating gate layer remaining; after the removing, forming a second dielectric layer over the first dielectric layer along the first sidewall and the second sidewall of the control gate, the second dielectric layer directly contacting an upper surface of the first portion of the floating gate layer, the first dielectric layer completely separating the second dielectric layer from the upper surface of the second portion of the floating gate layer; and after the forming the second dielectric layer, patterning the floating gate layer on the first side and the second side of the control gate to form a floating gate.