Semiconductor chip layout with staggered Tx and Tx data lines

摘要

A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.

主权项

1. An integrated circuit device comprising:
a first semiconductor die comprising;
a central axis dividing the first semiconductor die into a first portion and a second portion;a first serial interface located approximately at the central axis, the serial interface comprising a first transmitter port and a first receiver port;a first plurality of Tx data lines connected to the first transmitter port and extending away from the central axis, at least one Tx data line of the first plurality of Tx lines located in both the first portion and the second portion of the first semiconductor die; anda first plurality of Rx data lines connected to the first receiver port and extending away from the central axis, at least one Rx data line of the first plurality of Rx lines located in both the first portion and the second portion of the first semiconductor die.