Nanowire circuit architecture

摘要

A nanowire circuit architecture is presented. The technology comprises of nanowire transistors (8,9), and optionally nanowire capacitors (12) and nanowire resistors (11), that are integrated using two levels of interconnects only (1,2). Implementations of ring-oscillators, sample-and-hold circuits, and comparators may be realized in this nanowire circuit architecture. Circuit input and circuit output as well as the transistor connections within each circuit are provided in the two levels of interconnects (1,2).

主权项

1. A nanowire circuit comprising at least a first nanowire transistor, wherein the first nanowire transistor comprises a first nanowire protruding from a substrate, the first nanowire having a first wrap gate electrode arranged around a portion of its length, characterized in that two interconnects levels are used, one of which is a first interconnect level located on the substrate providing an electrode connected to one end of the first nanowire, and the first wrap gate electrode of the first nanowire is provided in one of the two interconnect levels and the first wrap gate electrode is electrically connected to the electrode located in the first interconnect level connected to one end of the first nanowire,
wherein the first wrap gate electrode is directly electrically connected to an electrode layer located on the substrate and directly electrically connected to the portion of the nanowire surrounded by the first wrap gate electrode.