Stack position determination in memory devices configured for stacked arrangements

摘要

Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.

主权项

1. A semiconductor memory device, comprising:
a) a plurality of comparators, wherein each comparator is configured to compare a first capacitance on a first pad against a second capacitance on a second pad; b) a plurality of latches coupled to outputs of the plurality of comparators, wherein each latch is configured to be set in response to a corresponding comparator output indicating that the first capacitance is greater than the second capacitance by at least a predetermined amount; c) a counter configured to count a number of the plurality of latches that are reset to determine a stack position identifier for the semiconductor memory device; and d) a register configured to store the stack position identifier on the semiconductor memory device.