发明名称 Method of fabricating semiconductor device
摘要 A method of fabricating a semiconductor device includes forming switching devices on a substrate. A lower structure is formed in the substrate having the switching devices. A lower conductive layer is formed on the lower structure. Sacrificial mask patterns are formed on the lower conductive layer. Lower conductive patterns are formed by etching the lower conductive layer using the sacrificial mask patterns as an etch mask. An interlayer insulating layer is formed on the substrate having the lower conductive patterns. Interlayer insulating patterns are formed by planarizing the interlayer insulating layer until the sacrificial mask patterns are exposed. Openings exposing the lower conductive patterns are formed by removing the exposed sacrificial mask patterns. Upper conductive patterns self-aligned with the lower conductive patterns are formed in the openings.
申请公布号 US8889543(B2) 申请公布日期 2014.11.18
申请号 US201313795807 申请日期 2013.03.12
申请人 Samsung Electronics Co., Ltd. 发明人 Baek Jong-Min;Park In-Sun;Lee Jong-Myeong;Hong Jong-Won;Kim Hei-Seung;Yoon Jung-Soo
分类号 H01L21/4763;H01L21/768 主分类号 H01L21/4763
代理机构 Volentine & Whitt, PLLC 代理人 Volentine & Whitt, PLLC
主权项 1. A method of fabricating a semiconductor device, comprising: forming switching devices on a substrate; forming a lower structure on the substrate having the switching devices; forming a lower conductive layer on the lower structure; forming sacrificial mask patterns on the lower conductive layer; forming lower conductive patterns by etching the lower conductive layer using the sacrificial mask patterns as an etch mask; forming an interlayer insulating layer on the substrate having the lower conductive patterns; forming interlayer insulating patterns by planarizing the interlayer insulating layer until the sacrificial mask patterns are exposed; forming openings exposing the lower conductive patterns by removing the exposed sacrificial mask patterns; and forming upper conductive patterns self-aligned with the lower conductive patterns in the openings.
地址 Suwon-si, Gyeonggi-do KR