Orthogonal variable spreading factor code sequence generation

摘要

An apparatus generally having a first circuit and a second circuit is disclosed. The first circuit may be configured to generate (i) a plurality of first code bits in response to an index value and (ii) a plurality of first intermediate bits in response to the index value. The first code bits may be generated in parallel with the first intermediate bits. The second circuit may be configured to generate a plurality of second code bits in response to all of (i) the index value, (ii) the first code bits and (iii) the first intermediate bits. A combination of the first code bits and the second code bits generally forms one of a plurality of orthogonal codes.

主权项

1. An apparatus comprising:
a first circuit configured to generate (i) a plurality of first code bits in response to an index value and (ii) a plurality of first intermediate bits in response to said index value, wherein (a) said first code bits are generated in parallel with said first intermediate bits, (b) said first code bits are generated separately from said first intermediate bits and (c) said first code bits are fewer in number than said first intermediate bits; and a second circuit configured to generate a plurality of second code bits in response to all of (i) said index value, (ii) said first code bits and (iii) said first intermediate bits, wherein a combination of said first code bits and said second code bits forms one of a plurality of orthogonal codes.