发明名称 |
Integrated electrostatic discharge (ESD) device |
摘要 |
A semiconductor device for ESD protection includes a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed within the substrate. The well region is characterized by a first depth. The device includes an MOS transistor, a first bipolar transistor, and a second bipolar transistor. The MOS transistor includes a first lightly doped drain (LDD) region of a second depth within the well region, and a drain region and an emitter region within in the first LDD region. The emitter region is characterized by a second conductivity type. The first bipolar transistor is associated with the emitter region, the first LDD region, and the well region, and is characterized by a first trigger voltage. The second bipolar transistor is associated with the first LDD region, the well region, and the substrate, and is characterized by a second trigger voltage. |
申请公布号 |
US8891213(B2) |
申请公布日期 |
2014.11.18 |
申请号 |
US201113244292 |
申请日期 |
2011.09.24 |
申请人 |
Semiconductor Manufacturing International (Shanghai) Corporation |
发明人 |
Liu Chi Kang;Yu Ta Lee;Li Quan |
分类号 |
H02H9/00;H01L27/02;H01L29/78;H02H3/22;H02H3/02;H02H3/08 |
主分类号 |
H02H9/00 |
代理机构 |
Kilpatrick Townsend and Stockton LLP |
代理人 |
Kilpatrick Townsend and Stockton LLP |
主权项 |
1. A bipolar ESD clamp apparatus, the apparatus comprising:
a p-type silicon substrate comprising a surface region; an N-well region within the substrate, the N-well region being characterized by a first depth; a p-type high-voltage lightly-doped-drain (LDD) region disposed completely within the N-well region; an N+ region disposed completely within the high voltage LDD region, the N+ region being connected to a pad structure; a P+ region within the high voltage LDD region, the P+ region being connected to the pad structure; wherein the high voltage LDD region, the N-well region, and the substrate are associated with a first bipolar transistor, the first bipolar transistor being characterized by a first trigger voltage, and wherein the N+ region, the high voltage LDD region, and the N-well region are associated with a second bipolar transistor, the second bipolar transistor being characterized by a second trigger voltage, wherein the high voltage LDD region extends a first emitter of the first bipolar transistor, and wherein the first emitter of the first bipolar transistor is coupled to the P+ region. |
地址 |
Shanghai CN |