Duty cycle correction circuit of delay locked loop and delay locked loop having the duty cycle correction circuit

摘要

A duty cycle correction circuit and a delay locked loop (DLL) including the duty cycle correction circuit, are capable of controlling their operation in order to correctly analyze the cause of generation of a duty cycle error when the duty cycle error is generated in the DLL. The duty cycle correction circuit selectively outputs to a DLL core duty cycle offset information for controlling a duty cycle of an internal clock signal synchronized to an external clock signal under the control of a switching control signal. The DLL corrects the duty cycle of a reference clock signal according to the duty cycle offset information, thereby outputting a reference clock signal having a 50% duty cycle.

主权项

1. A delay locked loop (DLL) comprising:
a DLL core adapted to receive an external clock signal and to generate an internal clock signal synchronized to the external clock signal; a buffer adapted to buffer the internal clock signal and to output differential reference clock signals; and a duty cycle correction circuit adapted to generate first control signals having desired offsets corresponding to differences in duty cycles of the differential reference clock signals, and to output the first control signals to the DLL core under the control of a switching control signal, wherein the DLL core corrects a duty cycle of the internal clock signal in response to the first control signals, wherein in a duty-cycle error analysis mode, the switching control signal selectively turns on and turns off the duty cycle correction circuit to inhibit output of the first control signals to the DLL core, wherein the duty cycle correction circuit comprises:
a differential amplifier having first and second input terminals and first and second differential output terminals, and adapted to receive the differential reference clock signals via the first and second input terminals, to amplify the differential reference clock signals, and to output the amplified differential reference clock signals via the first and second differential output terminals;a first transmission circuit connected between the first differential output terminal of the differential amplifier and a first node, and adapted to transmit to the first node a first one of the amplified differential reference clock signals appearing at the first differential output terminal of the differential amplifier;a second transmission circuit connected between the second differential output terminal of the differential amplifier and a second node, and adapted to transmit to the second node a second one of the amplified differential reference clock signals appearing at the second differential output terminal of the differential amplifier;a first storage unit connected between the first node and a ground voltage, and adapted to store a signal of the first node;a second storage unit connected between the second node and the ground voltage and adapted to store a signal of the second node; anda switching circuit connected between the first node and a first input terminal of the DLL core, and connected between the second node and a second input terminal of the DLL core, the switching circuit having a control terminal adapted to receive the switching control signal to selectively provide the signals of the first and second nodes to the first and second input terminals of the DLL core as the first control signals, and wherein the first transmission circuit is adapted to provide the first one of the amplified differential reference clock signals to the first node, and the second transmission circuit is adapted to provide the second one of the amplified differential reference clock signals to the second node, while the switching control signal has an activated state and while the switching control signal has a deactivated state.