Memory cell

摘要

Implementations disclosed herein may relate to a memory cell, such as a DRAM memory cell, for example.

主权项

1. A memory array comprising: at least a two-transistor DRAM memory cell, said memory cell comprising a charge storage device positioned over and coupled to a P-type MOS transistor and an N-type MOS transistor having a common electrical contact, said P-type and said N-type transistors respectively having a gate contact to accept logically complementary voltage signal levels so that during operation of said memory cell an increase or a decrease in charge stored by said charge storage device takes place.