发明名称 Scan cell use with reduced power consumption
摘要 Selective blocking is applied to discrete segments of scan chains in the integrated circuit device. In some implementations, locking components associated with the scan segments are selectively activated according to blocking data incorporated in test pattern data. In other implementations, selective blocking is applied to the scan cells identified as causing the highest power consumption. Selective incorporation of blocking components in an integrated circuit device is based on statistical estimation of scan cell transition rates. When the blocking components are enabled, pre-selected signal values are presented to the functional logic of the integrated circuit device. At the same time, propagation of output value transitions that may take place in the scan cells is prevented.
申请公布号 US8890563(B2) 申请公布日期 2014.11.18
申请号 US200912991688 申请日期 2009.05.07
申请人 Mentor Graphics Corporation 发明人 Lin Xijiang;Rajski Janusz
分类号 H03K19/00;G01R31/28;G01R31/3185 主分类号 H03K19/00
代理机构 代理人
主权项 1. An integrated circuit, comprising: a plurality of scan cells configured as one or more scan chains; a circuit configured as functional logic and coupled to the one or more scan chains; a plurality of blocking components coupled to the scan cells and configured to isolate scan cell outputs from the functional logic; and a block enable devices coupled to the plurality of blocking components and configured to control operation of the plurality of blocking components during a capture mode of operation.
地址 Wilsonville OR US