Parasitic component library and method for efficient circuit design and simulation using the same

摘要

A method for circuit design includes a parasitic aware library embedded with one or more parameterized cells. The parasitic aware library is used to insert nets representing some but not all parasitic effects of a circuit into a circuit schematic enabling a single circuit schematic to be used for simulation of the circuit, parasitic verification of the circuit and LVS (Layout Versus Schematic) check. Only the single circuit schematic is required for the circuit design process and to form a mask set. Critical paths of the single circuit schematic are identified and parasitic effects are extracted and inserted into the schematic, enabling a pre-estimation of parasitic verification to be carried out and the LVS check to be carried out using a circuit schematic with some parasitic effects prior to the post-layout simulation in which all parasitic components of the layout are included.

主权项

1. A method for semiconductor device circuit design using a single circuit schematic for simulation, parasitic verification, and comparison to a layout, said method comprising:
providing a circuit schematic without parasitic effects to a computer; inserting some but not all parasitic effects into said circuit schematic at identified circuit paths through dynamic extraction, using said computer; simulating operation of said circuit using said circuit schematic with said inserted some but not all parasitic effects using said computer; generating a complete layout of said semiconductor device circuit using said circuit schematic with said inserted some but not all parasitic effects if said circuit schematic with said inserted some but not all parasitic effects, operates according to specification in said simulating, using said computer; comparing said complete layout to said circuit schematic with said inserted some but not all parasitic effects by performing an LVS (Layout Versus Schematic) check using said computer; inserting all said parasitic effects of said complete layout, into said circuit schematic thereby providing a netlist of a parasitic effects containing circuit; and carrying out a post-layout circuit simulation of said parasitic effects containing circuit using said netlist of said parasitic effects containing circuit.