Communications system for implementation of synchronous, multichannel, galvanically isolated instrumentation devices

摘要

An apparatus and method for synchronous communications using a serial data stream employs a housing with a controller and a back plane. The housing accepts one or more modules for interconnection with the back plane. The back plane distributes power to the modules and provides a communication link from the controller to each module. Each communication link includes a data out line, a data in line and a clock line, where each clock line is derived from one clock source.

主权项

1. A method for synchronous triggering of events in a plurality of modules, the method comprising:
providing each module with a corresponding communications link to a common controller, each communication link comprising a corresponding data out line and a corresponding clock line carrying a corresponding clock signal, wherein all of the clock signals are derived from a single, common, clock source; independently selectively enabling and disabling each of the clock signals at the controller; transmitting from the controller to a first one of the modules over the corresponding clock line for the first module the corresponding clock signal, and transmitting from the controller to the first module over the corresponding data out tine for the first module a first send packet synchronous with the clock source, wherein the first send packet contains at least one bit position defined as a trigger bit for the first module; transmitting from the controller to a second one of the modules over the corresponding clock line for the second module the corresponding clock signal, and transmitting from the controller to the second module over the corresponding data out line for the second module a second send packet synchronous with the clock source, wherein the second send packet contains at least one bit position defined as a trigger bit for the second module; triggering an event in the first module upon receipt by the first module of the trigger bit in the first send packet; and triggering an event in the second module upon receipt by the second module of the trigger bit in the second send packet.