发明名称 MULTILAYER SUBSTRATE AND MANUFACTURING METHOD THEREFOR
摘要 <p>PROBLEM TO BE SOLVED: To suppress short circuit between interconnections due to voids generated between inner layer interconnections, in a multilayer board produced by laminating a build-up layer, consisting of a prepreg, on the outer surface of a core layer as an insulation layer, and then sealing a plurality of inner layer interconnections provided on the outer surface with resin of the build-up layer.SOLUTION: The part positioned between a plurality of inner layer interconnections 51, 52, out of the front and back surfaces 20a, 20b of a core layer 20, are uneven surfaces 21a, 21b having a surface roughness larger than that of a part where the plurality of inner layer interconnections 51, 52 are positioned.</p>
申请公布号 JP2014216566(A) 申请公布日期 2014.11.17
申请号 JP20130094377 申请日期 2013.04.26
申请人 DENSO CORP 发明人 YABUTA EIJI;KISHIMOTO KEIJI
分类号 H05K3/46 主分类号 H05K3/46
代理机构 代理人
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