SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME

摘要

A semiconductor memory device includes a memory cell array, an error correction circuit and an input/output (I/O) gating circuit. The error correction circuit receives a first main data including a plurality of unit data, generates a second main data and parity data based on the first main data and initial data pre-stored in the memory cell array, and provides a code word including the second main data and the parity data. The I/O gating circuit reads the initial data with respect to unit data not to be written to the memory cell array among the second main data and provides the read initial data to the error correction circuit, and receives the initial data corrected by the error correction circuit and rewrites the received initial data in the memory cell array, when a partial update operation of writing part of the second main data in the memory cell array is performed.