| 发明名称 |
CHIP ARRANGEMENT, AND METHOD FOR FORMING A CHIP ARRANGEMENT |
| 摘要 |
A chip arrangement may include: a chip including a plurality of electrical nets, wherein each electrical net includes at least one bonding pad; and a plurality of pillars formed on the at least one bonding pad of a majority of the plurality of electrical nets, wherein the plurality of pillars may be configured to connect the at least one bonding pad of the majority of the plurality of electrical nets to a chip-external connection region. |
| 申请公布号 |
US2014332953(A1) |
申请公布日期 |
2014.11.13 |
| 申请号 |
US201313892367 |
申请日期 |
2013.05.13 |
| 申请人 |
Infineon Technologies AG |
发明人 |
Ossimitz Peter;Bauer Robert;Jacobs Tobias |
| 分类号 |
H01L23/498;H01L21/768 |
主分类号 |
H01L23/498 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A chip arrangement, comprising:
a chip comprising a plurality of electrical nets, wherein each electrical net comprises at least one bonding pad; and a plurality of pillars formed on the at least one bonding pad of a majority of the plurality of electrical nets, wherein the plurality of pillars is configured to connect the at least one bonding pad of the majority of the plurality of electrical nets to a chip-external connection region. |
| 地址 |
Neubiberg DE |
