| 摘要 |
In a semiconductor device which conducts multilevel writing operation and a driving method thereof, a signal line for controlling on/off of a writing transistor for conducting a writing operation on a memory cell using a transistor including an oxide semiconductor layer is disposed along a bit line, and a multilevel writing operation is conducted with use of, also in a writing operation, a voltage which is applied to a capacitor at a reading operation. Because an oxide semiconductor material that is a wide gap semiconductor capable of sufficiently reducing off-state current of a transistor is used, data can be held for a long period. |
| 主权项 |
1. A semiconductor device comprising:
a source line; a bit line; first to m-th word lines (m is a natural number greater than or equal to 2); a first signal line; a second signal line; a selection line; first to m-th memory cells connected in series between the source line and the bit line; and a selection transistor having a gate electrically connected to the selection line; each of the first to m-th memory cells comprising: a first transistor including a first gate, a first source, and a first drain; a second transistor including a second gate, a second source, and a second drain; and a capacitor, wherein the second transistor includes an oxide semiconductor layer, wherein the source line is electrically connected to the first source of the m-th memory cell through the selection transistor, wherein the bit line is electrically connected to the first drain of the first memory cell, wherein the first signal line is electrically connected to the second drain of the first to m-th memory cells wherein the second signal line is electrically connected to the second gate of the first to m-th memory cells, wherein the first drain of the l-th (l is a natural number of from 2 to m) memory cell is electrically connected to the first source of the (l−1)-th memory cell, wherein the k-th (k is a natural number of from 1 to m) word line is electrically connected to one terminal of the capacitor of the k-th memory cell, and wherein the second drain of the l-th memory cell is electrically connected to the first gate of the (l−1)-th memory cell, the second source of the (l−1)-th memory cell and the other terminal of the capacitor of the (l−1)-th memory cell. |
