发明名称 DESIGN SUPPORT DEVICE, DESIGN SUPPORT METHOD, AND COMPUTER-READABLE RECORDING MEDIUM HAVING STORED THEREIN DESIGN SUPPORT PROGRAM
摘要 When a sequential circuit to which a clock signal distributed by a first buffer included in a clock distribution circuit is input is added, in a case where a plurality of other sequential circuits are connected to the first buffer, a processor determines whether or not a distance between the sequential circuit to be added and the first buffer is between a maximum value and a minimum value of distances between the first buffer and the plurality of other sequential circuits based on the physical design data stored in the memory, and, as a result of the determination, in a case where the distance between the sequential circuit to be added and the first buffer is between the maximum value and the minimum value, the processor performs wiring processing of the clock signal supplied from the first buffer for the sequential circuit to be added.
申请公布号 US2014337657(A1) 申请公布日期 2014.11.13
申请号 US201414341881 申请日期 2014.07.28
申请人 FUJITSU LIMITED 发明人 Watanabe Yuuki;Amano Yasuo;Arayama Masashi
分类号 G06F1/06 主分类号 G06F1/06
代理机构 代理人
主权项 1. A design support device comprising: a memory configured to store physical design data of a circuit that includes a clock distribution circuit having a buffer; and a processor, wherein the processor, when a sequential circuit to which a clock signal distributed by a first buffer included in the clock distribution circuit is input is added, in a case where a plurality of other sequential circuits are connected to the first buffer, determines whether or not a distance between the sequential circuit to be added and the first buffer is between a maximum value and a minimum value of distances between the first buffer and the plurality of other sequential circuits based on the physical design data stored in the memory, and wherein, as a result of the determination, in a case where the distance between the sequential circuit to be added and the first buffer is between the maximum value and the minimum value, the processor performs wiring processing of the clock signal supplied from the first buffer for the sequential circuit to be added.
地址 Kawasaki-shi JP