HIGH VOLTAGE GATE FORMATION

摘要

Embodiments described herein generally relate to methods of manufacturing charge-trapping memory by patterning the high voltage gates before other gates are formed. One advantage of such an approach is that a thin poly layer may be used to form memory and low voltage gates while protecting high voltage gates from implant penetration. One approach to accomplishing this is to dispose the layer of poly, and then dispose a mask and a thick resist to pattern the high voltage gates. In this manner, the high voltage gates are formed before either the low voltage gates or the memory cells.

主权项

1. A semiconductor device having a memory region, a first substrate region, and a second substrate region, the semiconductor device comprising:
first gates in the first substrate region; second gates in the second substrate region; third gates in the memory region; and fourth gates in the memory region, wherein each fourth gate is formed adjacent to a corresponding third gate, and wherein a sidewall of each of the fourth gates is formed before one or more sidewalls of the second gates.